199 lines
9.1 KiB
C
199 lines
9.1 KiB
C
#ifndef _REG_CACHE_H_
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#define _REG_CACHE_H_
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#include "reg_base.h"
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//================================
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//BLOCK CACHE define
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#define CACHE_BASE ((uint32_t)0x19000000)
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#define CACHE_CCR_ADDR_OFFSET 0x000
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#define CACHE_CCFR_ADDR_OFFSET 0x004
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#define CACHE_CIR_ADDR_OFFSET 0x008
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#define CACHE_CRCR0_ADDR_OFFSET 0x00c
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#define CACHE_CRCR1_ADDR_OFFSET 0x010
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#define CACHE_CRCR2_ADDR_OFFSET 0x014
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#define CACHE_CRCR3_ADDR_OFFSET 0x018
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//================================
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//BLOCK CACHE reg struct define
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typedef union //0x000
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{
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struct
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{
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uint32_t CACHE_EN: 1; // bit0 ---
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// 0: cache disable
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// 1: cache enable
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uint32_t RESERVED: 31; // bit[31:1]
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};
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uint32_t Word;
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} CACHE_CCR_TypeDef; //0x000
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//================================
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#define CACHE_CACHE_EN_POS 0
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#define CACHE_RESERVED_LSB 1
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#define CACHE_RESERVED_WIDTH 31
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//================================
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typedef union //0x004
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{
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struct
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{
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uint32_t RSV_NOUSE1: 3; // bit[2:0] --- Ignore me
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uint32_t CACHE_INST_DATA: 1; // bit3 the control bits of cached data type configuration
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// 0: only instruction data can be cached
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// 1: both instruction and common data can be cached
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// note: it requires that arb_xx_hprot[0] indicate whether this access is instruction data
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// request or common data request
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uint32_t RSV_END: 28; // bit[31:4]
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};
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uint32_t Word;
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} CACHE_CCFR_TypeDef; //0x004
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//================================
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#define CACHE_CACHE_INST_DATA_POS 3
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//================================
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typedef union //0x008
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{
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struct
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{
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uint32_t INV_ALL: 1; // bit0 --- The control bit of invalid all cache lines operation. Set this
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// bit to start an invalid all cache lines operation, and the bit
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// will be cleared when the operation is done.
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uint32_t INV_ONE: 1; // bit1 --- The control bit of invalid one cache line operation. Set this
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// bit to start an invalid one cache line operation, and the bit
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// will be cleared when the operation is done.
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uint32_t RSV_NOUSE1: 2; // bit[3:2] --- Ignore me
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uint32_t INV_ADDR: 28; // bit[31:4]--- The high bits of cache line address of invalid one cache
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// line operation.
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};
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uint32_t Word;
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} CACHE_CIR_TypeDef; //0x008
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//================================
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#define CACHE_INV_ALL_POS 0
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#define CACHE_INV_ONE_POS 1
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#define CACHE_INV_ADDR_LSB 4
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#define CACHE_INV_ADDR_WIDTH 28
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//================================
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typedef union //0x00c
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{
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struct
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{
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uint32_t CRCR0_EN: 1; // bit0 --- Cache region enable bit. Only enable bit is set that the
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// cacheable region is valid.
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uint32_t SIZE: 5; // bit[5:1] --- These control bits indicate the size of cacheable region.
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// Detail is shown below table.
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uint32_t RSV_NOUSE1: 4; // bit[9:6] --- Ignore me
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uint32_t BASE_ADDR: 22; // bit[31:10]-- High 22 bits of base address of cacheable region.
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};
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uint32_t Word;
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} CACHE_CRCR0_TypeDef; //0x00c
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//================================
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#define CACHE_CRCR0_EN_POS 0
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#define CACHE_SIZE_LSB 1
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#define CACHE_SIZE_WIDTH 5
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#define CACHE_BASE_ADDR_LSB 10
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#define CACHE_BASE_ADDR_WIDTH 22
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//================================
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typedef union //0x010
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{
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struct
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{
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uint32_t CRCR1_EN: 1; // bit0 --- Cache region enable bit. Only enable bit is set that the
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// cacheable region is valid.
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uint32_t SIZE: 5; // bit[5:1] --- These control bits indicate the size of cacheable region.
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// Detail is shown below table.
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uint32_t RSV_NOUSE1: 4; // bit[9:6] --- Ignore me
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uint32_t BASE_ADDR: 22; // bit[31:10]-- High 22 bits of base address of cacheable region.
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};
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uint32_t Word;
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} CACHE_CRCR1_TypeDef; //0x010
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//================================
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#define CACHE_CRCR1_EN_POS 0
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#define CACHE_SIZE_LSB 1
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#define CACHE_SIZE_WIDTH 5
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#define CACHE_BASE_ADDR_LSB 10
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#define CACHE_BASE_ADDR_WIDTH 22
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//================================
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typedef union //0x014
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{
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struct
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{
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uint32_t CRCR2_EN: 1; // bit0 --- Cache region enable bit. Only enable bit is set that the
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// cacheable region is valid.
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uint32_t SIZE: 5; // bit[5:1] --- These control bits indicate the size of cacheable region.
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// Detail is shown below table.
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uint32_t RSV_NOUSE1: 4; // bit[9:6] --- Ignore me
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uint32_t BASE_ADDR: 22; // bit[31:10]-- High 22 bits of base address of cacheable region.
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};
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uint32_t Word;
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} CACHE_CRCR2_TypeDef; //0x014
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//================================
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#define CACHE_CRCR2_EN_POS 0
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#define CACHE_SIZE_LSB 1
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#define CACHE_SIZE_WIDTH 5
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#define CACHE_BASE_ADDR_LSB 10
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#define CACHE_BASE_ADDR_WIDTH 22
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//================================
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typedef union //0x018
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{
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struct
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{
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uint32_t CRCR3_EN: 1; // bit0 --- Cache region enable bit. Only enable bit is set that the
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// cacheable region is valid.
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uint32_t SIZE: 5; // bit[5:1] --- These control bits indicate the size of cacheable region.
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// Detail is shown below table.
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uint32_t RSV_NOUSE1: 4; // bit[9:6] --- Ignore me
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uint32_t BASE_ADDR: 22; // bit[31:10]-- High 22 bits of base address of cacheable region.
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};
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uint32_t Word;
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} CACHE_CRCR3_TypeDef; //0x018
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//================================
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#define CACHE_CRCR3_EN_POS 0
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#define CACHE_SIZE_LSB 1
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#define CACHE_SIZE_WIDTH 5
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#define CACHE_BASE_ADDR_LSB 10
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#define CACHE_BASE_ADDR_WIDTH 22
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//================================
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//================================
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//BLOCK CACHE top struct define
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typedef struct
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{
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__IO CACHE_CCR_TypeDef CCR ; // 0x000,
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// This register is responsible for making cache enable or disable.
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__IO CACHE_CCFR_TypeDef CCFR ; // 0x004,
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// This register controls the software configuration of cache. Note: The cache should be disabled before
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// changing the configuration, or fatal errors may occur.
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__IO CACHE_CIR_TypeDef CIR ; // 0x008,
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// This register controls the invalid operation for cache, including invalid one cache line and invalid all.
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__IO CACHE_CRCR0_TypeDef CRCR0 ; // 0x00c,
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// This register controls the cacheable region. Request address must locate in the cacheable region and this
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// region is enabled, or read data will not be cached.
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__IO CACHE_CRCR1_TypeDef CRCR1 ; // 0x010,
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__IO CACHE_CRCR2_TypeDef CRCR2 ; // 0x014,
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__IO CACHE_CRCR3_TypeDef CRCR3 ; // 0x018,
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} CACHE_TypeDef;
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#define CACHE (( CACHE_TypeDef *) CACHE_BASE)
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#endif
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